Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL

This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT\u27s for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and operation mode. The static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process

Design and implementation of an asynchronous NULL Convention Logic (NCL) FPGA

This Master\u27s thesis outlines the design of a completely asynchronous Field Programmable Gate Array (FPGA) for implementing NULL Convention Logic (NCL) digital circuits. The proposed design uses four Configurable Logic Blocks (CLB), each of which in turn is designed using four Logic Elements (LE) to implement NCL logic function. Each LE can be configured to function as any one of the 27 fundamental NCL gates. A Logic Element is designed by concatenating a Look-Up-Table (LUT) with a pull-up pull-down transistor chain and a hysteresis loop. The interconnections and the switch box are designed using pass transistors and SRAM. In this thesis, a 4-input Look-Up Table (LUT) based 16-gate FPGA specifically for NCL circuits was designed and successfully programmed as a dual-rail non-pipelined 4-bit NCL register. The design was first created using the schematic capture, followed by layout or the physical level designs subsequent to successful simulation. The NCL FPGA is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process. The size of FPGAs is now more than 1 million equivalent gates, making them a viable alternative to custom design for all but the most complex processors. FPGAs are relatively low-cost and are reconfigurable, making them perfect for prototyping, as well as implementing the final design, especially for low volume production. To compete with this cheap, reconfigurable synchronous implementation, an NCL-specific FPGA is needed, such that NCL circuits can be implemented without necessitating a prohibitively expensive full-custom design --Abstract, page iii

Design of a Flood Prediction System

This paper explains the chip design of a flood prediction system based on piezoelectric pressure sensors. The sensors are placed at different water levels and can dependably predict the occurrence of a flood. The main criteria considered in the design of the system are low cost, low power consumption, ease of installation, autonomy, reliability, and most importantly, provision of early alerts. Predicting the flood before its actual occurrence can buy sufficient time for residents to evacuate nearby areas, preventing loss of life and property. The design has been prototyped on Altera\u27s Cyclone DE2 FPGA board

Design and Implementation of FPGA Configuration Logic Block using Asynchronous Semi-Static NCL Circuits

This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT\u27s for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and Operation mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process